Statistical Estimation of the Switching Activity in VLSI Circuits

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity thit has been called the transition density. This paper presents a statisticil simuiation technique to estimate individual node transition densities in combinational logic circuits. The strength of this approach is that the desired accuracy and confidence canbe specified up-front by the user. Another key feature is the classification of nodes into two categories: regularand low-density nodes. Regular-density nodes are certified with user-specified percentage eruor and confidence levels. Low-density nodes are certified with an absolute error, with the same confidence. This speeds convergence while sacrificing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.